Sciweavers

138 search results - page 26 / 28
» Compiled-code-based simulation with timing verification
Sort
View
SENSYS
2005
ACM
14 years 1 months ago
Estimating clock uncertainty for efficient duty-cycling in sensor networks
Radio duty cycling has received significant attention in sensor networking literature, particularly in the form of protocols for medium access control and topology management. Whi...
Saurabh Ganeriwal, Deepak Ganesan, Hohyun Shim, Vl...
ATAL
2009
Springer
14 years 2 months ago
Graph-based methods for the analysis of large-scale multiagent systems
Multiagent systems are often characterized by complex, and sometimes unpredictable interactions amongst their autonomous components. While these systems can provide robust and sca...
Wilbur Peng, William Krueger, Alexander Grushin, P...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 1 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
DSN
2002
IEEE
14 years 15 days ago
Ditto Processor
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 12 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli