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SAMOS
2010
Springer
13 years 8 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
ICML
2007
IEEE
14 years 10 months ago
Parameter learning for relational Bayesian networks
We present a method for parameter learning in relational Bayesian networks (RBNs). Our approach consists of compiling the RBN model into a computation graph for the likelihood fun...
Manfred Jaeger
SIGSOFT
2002
ACM
14 years 10 months ago
Using redundancies to find errors
This paper explores the idea that redundant operations, like type errors, commonly flag correctness errors. We experimentally test this idea by writing and applying four redundanc...
Yichen Xie, Dawson R. Engler
ICFP
2006
ACM
14 years 9 months ago
The development of Chez Scheme
Chez Scheme is now over 20 years old, the first version having been released in 1985. This paper takes a brief look back on the history of Chez Scheme's development to explor...
R. Kent Dybvig
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 6 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome