Sciweavers

118 search results - page 18 / 24
» Compiler Support for Exploiting Coarse-Grained Pipelined Par...
Sort
View
95
Voted
ITC
2000
IEEE
110views Hardware» more  ITC 2000»
15 years 7 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu
167
Voted
WOMPAT
2004
Springer
15 years 8 months ago
Dragon: A Static and Dynamic Tool for OpenMP
A program analysis tool can play an important role in helping users understand and improve OpenMP codes. Dragon is a robust interactive program analysis tool based on the Open64 co...
Oscar Hernandez, Chunhua Liao, Barbara M. Chapman
139
Voted
TPDS
2010
144views more  TPDS 2010»
15 years 1 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 9 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
PC
2007
343views Management» more  PC 2007»
15 years 2 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...