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» Compiler Technology for Two Novel Computer Architectures
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CGO
2007
IEEE
14 years 2 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 2 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
INFOSCALE
2007
ACM
13 years 10 months ago
Load-balancing and caching for collection selection architectures
— To address the rapid growth of the Internet, modern Web search engines have to adopt distributed organizations, where the collection of indexed documents is partitioned among s...
Diego Puppin, Fabrizio Silvestri, Raffaele Perego,...
ISCA
2008
IEEE
107views Hardware» more  ISCA 2008»
14 years 2 months ago
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
This paper seeks to understand and design nextgeneration servers for emerging “warehousecomputing” environments. We make two key contributions. First, we put together a detail...
Kevin T. Lim, Parthasarathy Ranganathan, Jichuan C...
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
14 years 2 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...