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» Compiler-managed partitioned data caches for low power
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CASES
2006
ACM
14 years 1 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...
IPCCC
2006
IEEE
14 years 1 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
SCOPES
2004
Springer
14 years 24 days ago
Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...
Heiko Falk, Manish Verma
DAWAK
2005
Springer
14 years 1 months ago
Nearest Neighbor Search on Vertically Partitioned High-Dimensional Data
Abstract. In this paper, we present a new approach to indexing multidimensional data that is particularly suitable for the efficient incremental processing of nearest neighbor quer...
Evangelos Dellis, Bernhard Seeger, Akrivi Vlachou
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 1 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...