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» Compiler-managed partitioned data caches for low power
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ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
13 years 11 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
14 years 1 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
CF
2005
ACM
13 years 9 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 7 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
CASES
2001
ACM
13 years 11 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu