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CASES
2004
ACM
13 years 11 months ago
Translating affine nested-loop programs to process networks
New heterogeneous multiprocessor platforms are emerging that are typically composed of loosely coupled components that exchange data using programmable interconnections. The compon...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
ARC
2007
Springer
150views Hardware» more  ARC 2007»
13 years 11 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
MAM
2007
157views more  MAM 2007»
13 years 7 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
FPL
2009
Springer
149views Hardware» more  FPL 2009»
14 years 8 days ago
Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space
Commercial SRAM-based FPGAs have the potential to provide aerospace applications with the necessary performance to meet next-generation mission requirements. However, the suscepti...
Adam Jacobs, Alan D. George, Grzegorz Cieslewski
ATS
2004
IEEE
109views Hardware» more  ATS 2004»
13 years 11 months ago
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterj...