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HIPC
2000
Springer
13 years 11 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 9 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
FPL
2011
Springer
203views Hardware» more  FPL 2011»
12 years 7 months ago
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms
Abstract—In the clinical applications, medical image registrations on the images taken from different times and/or through different modalities are needed in order to have an obj...
Jason Cong, Muhuan Huang, Yi Zou
VISUALIZATION
2003
IEEE
14 years 1 months ago
Fast Volume Segmentation With Simultaneous Visualization Using Programmable Graphics Hardware
Segmentation of structures from measured volume data, such as anatomy in medical imaging, is a challenging data-dependent task. In this paper, we present a segmentation method tha...
Anthony Sherbondy, Michael Houston, Sandy Napel
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon