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ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
14 years 4 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
ERSA
2009
131views Hardware» more  ERSA 2009»
13 years 5 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
13 years 7 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
FPL
2008
Springer
175views Hardware» more  FPL 2008»
13 years 9 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
14 years 2 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...