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» Compiling Process Graphs into Executable Code
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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 4 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
ICSM
2006
IEEE
14 years 3 months ago
Source-Level Linkage: Adding Semantic Information to C++ Fact-bases
Facts extracted from source code have been used to support a variety of software engineering activities, ranging from architectural understanding, through detection of design patt...
Daqing Hou, H. James Hoover
MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
14 years 3 months ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
PLDI
2003
ACM
14 years 3 months ago
Static array storage optimization in MATLAB
An adaptation of the classic register allocation algorithm to the problem of array storage optimization in MATLAB is presented. The method involves the decomposition of an interfe...
Pramod G. Joisha, Prithviraj Banerjee
DAC
2009
ACM
14 years 10 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...