Sciweavers

500 search results - page 66 / 100
» Compiling SA-C Programs to FPGAs: Performance Results
Sort
View
ASPLOS
2011
ACM
14 years 7 months ago
On-the-fly elimination of dynamic irregularities for GPU computing
The power-efficient massively parallel Graphics Processing Units (GPUs) have become increasingly influential for scientific computing over the past few years. However, their ef...
Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Kai Tian, ...
TJS
2002
83views more  TJS 2002»
15 years 3 months ago
An I/O-Conscious Tiling Strategy for Disk-Resident Data Sets
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Due ...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
LCTRTS
2007
Springer
15 years 10 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
CODES
2004
IEEE
15 years 8 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
AADEBUG
2005
Springer
15 years 9 months ago
Automated bug isolation via program chipping
This paper introduces program chipping, a simple yet effective technique to isolate bugs. This technique automatically removes or chips away parts of a program so that the part t...
Chad D. Sterling, Ronald A. Olsson