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DATE
2004
IEEE
158views Hardware» more  DATE 2004»
14 years 1 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
AIPR
2008
IEEE
14 years 2 days ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
ISPA
2005
Springer
14 years 3 months ago
Next Generation Networks Architecture and Layered End-to-End QoS Control
Next-generation network (NGN) is a new concept and becoming more and more important for future telecommunication networks. This paper illustrates five function layers of NGN archit...
Weijia Jia, Bo Han, Ji Shen, Haohuan Fu
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 3 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
IPPS
1999
IEEE
14 years 2 months ago
A new Architecture for Multihop Optical Networks
Multihop lightwave networks are becoming increasingly popular in optical networks. It is attractive to consider regular graphs as the logical topology for a multihop network, due t...
Arunita Jaekel, Subir Bandyopadhyay, Abhijit Sengu...