1198 search results - page 26 / 240 » Compiling for EDGE Architectures |
ICCD
1993
IEEE
14 years 28 days ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
HOTOS
2009
IEEE
14 years 20 days ago
2009
IEEE
In this paper, we propose FLUXO, a system that separates an Internet service's logical functionality from the architectural decisions made to support performance, scalability...
DAC
1995
ACM
14 years 10 days ago
1995
ACM
Abstract—We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those w...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--Multicore shared-memory architectures are becoming prevalent but bring many programming challenges. Among the biggest is non-determinism: the output of the program does n...
ACMSE
2011
ACM
12 years 8 months ago
2011
ACM
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...