Sciweavers

1198 search results - page 2 / 240
» Compiling for EDGE Architectures
Sort
View
IEEEPACT
2000
IEEE
13 years 12 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
IPPS
2003
IEEE
14 years 24 days ago
The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
J. Eliot B. Moss, Charles C. Weems, Timothy Richar...
IEEEPACT
2003
IEEE
14 years 24 days ago
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, C...
CAMP
2000
IEEE
13 years 12 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada