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MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
14 years 1 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
SAC
2009
ACM
14 years 3 months ago
Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Nalini Vasudevan, Stephen A. Edwards
SIGPLAN
2008
13 years 8 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
DATE
2000
IEEE
137views Hardware» more  DATE 2000»
14 years 1 months ago
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr
ESOP
1992
Springer
14 years 27 days ago
A Provably Correct Compiler Generator
We have designed, implemented, and proved the correctness of a compiler generator that accepts action semantic descriptions of imperative programming languages. The generated comp...
Jens Palsberg