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DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 3 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
14 years 3 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
ICS
1998
Tsinghua U.
14 years 1 months ago
High-level Management of Communication Schedules in HPF-like Languages
The goal of High Performance Fortran (HPF) is to "address the problems of writing data parallel programs where the distribution of data affects performance", providing t...
Siegfried Benkner, Piyush Mehrotra, John Van Rosen...
PLDI
2005
ACM
14 years 2 months ago
Programming ad-hoc networks of mobile and resource-constrained devices
Ad-hoc networks of mobile devices such as smart phones and PDAs represent a new and exciting distributed system architecture. Building distributed applications on such an architec...
Yang Ni, Ulrich Kremer, Adrian Stere, Liviu Iftode
LCTRTS
2009
Springer
14 years 3 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...