Sciweavers

1198 search results - page 89 / 240
» Compiling for EDGE Architectures
Sort
View
HPCA
2011
IEEE
13 years 21 days ago
Checked Load: Architectural support for JavaScript type-checking on mobile processors
Dynamic languages such as Javascript are the de-facto standard for web applications. However, generating efficient code for dynamically-typed languages is a challenge, because it...
Owen Anderson, Emily Fortuna, Luis Ceze, Susan Egg...
LCPC
2004
Springer
14 years 2 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
CISIS
2010
IEEE
14 years 2 months ago
Study of Variations of Native Program Execution Times on Multi-Core Architectures
Abstract—Program performance optimisations, feedbackdirected iterative compilation and auto-tuning systems [1] all assume a fixed estimation of execution time given a fixed inp...
Abdelhafid Mazouz, Sid Ahmed Ali Touati, Denis Bar...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ICCD
2000
IEEE
159views Hardware» more  ICCD 2000»
14 years 1 months ago
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...
Deependra Talla, Lizy Kurian John, Viktor S. Lapin...