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ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
14 years 2 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
ASPLOS
1991
ACM
14 years 1 months ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
VEE
2005
ACM
143views Virtualization» more  VEE 2005»
14 years 3 months ago
Optimized interval splitting in a linear scan register allocator
We present an optimized implementation of the linear scan register allocation algorithm for Sun Microsystems’ Java HotSpotTM client compiler. Linear scan register allocation is ...
Christian Wimmer, Hanspeter Mössenböck
CODES
2001
IEEE
14 years 1 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
ENTCS
2002
166views more  ENTCS 2002»
13 years 9 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...