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DAC
2002
ACM
16 years 5 months ago
Compiler-directed scratch pad memory hierarchy design and management
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
Mahmut T. Kandemir, Alok N. Choudhary
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 4 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
IEEEPACT
2006
IEEE
15 years 10 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
CF
2010
ACM
15 years 9 months ago
ERBIUM: a deterministic, concurrent intermediate representation for portable and scalable performance
Tuning applications for multi-core systems involve subtle concepts and target-dependent optimizations. New languages are being designed to express concurrency and locality without...
Cupertino Miranda, Philippe Dumont, Albert Cohen, ...
SAC
2006
ACM
15 years 4 months ago
Efficient first-class generics on stock Java virtual machines
The second-class formulation of generics in Java 5.0 discards generic type information during compilation. As a result, Java 5.0 prohibits run-time type-dependent operations, gene...
James Sasitorn, Robert Cartwright