1133 search results - page 107 / 227 » Compiling for Speculative Architectures |
113
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ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
141
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MICRO
1994
IEEE
15 years 8 months ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
137
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DAC
2012
ACM
13 years 6 months ago
2012
ACM
Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controller...
124
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ISPASS
2007
IEEE
15 years 10 months ago
2007
IEEE
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
142
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CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...