Run-time power-down strategies for real-time SDRAM memory controllers

Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controllers, power-down mechanisms could impact both the guaranteed bandwidth and the memory latency bounds. This calls for power-down strategies that can hide or bound the performance loss, making run-time memory power-down feasible for real-time applications. In this paper, we propose two such strategies that reduce memory energy consumption and yet guarantee realtime memory performance. One provides significant energy savings without impacting the guaranteed bandwidth and latency bounds. The other provides higher energy savings with marginally increased latency bounds, while still preserving the guaranteed bandwidth provided by real-time memory controllers. We also present an algorithm to select the most energy-efficient power-down mode at run-time. We experimentally evaluate the two strategies at run-time by execu...

• Type: Journal
• Year: 2012
• Where: DAC
• Authors: Karthik Chandrasekar 0001, Benny Akesson, Kees Goossens
• Keywords: Computer Architecture, DAC 2012, Memory Controllers, Memory Latency, Time Memory