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ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
15 years 8 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
ASPLOS
1991
ACM
15 years 7 months ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
VEE
2005
ACM
143views Virtualization» more  VEE 2005»
15 years 9 months ago
Optimized interval splitting in a linear scan register allocator
We present an optimized implementation of the linear scan register allocation algorithm for Sun Microsystems’ Java HotSpotTM client compiler. Linear scan register allocation is ...
Christian Wimmer, Hanspeter Mössenböck
149
Voted
CODES
2001
IEEE
15 years 7 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
POPL
2009
ACM
15 years 11 months ago
The semantics of power and ARM multiprocessor machine code
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets...
Jade Alglave, Anthony C. J. Fox, Samin Ishtiaq, Ma...