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DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 10 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
ASPLOS
2006
ACM
15 years 10 months ago
Tartan: evaluating spatial computation for whole program execution
Spatial Computing (SC) has been shown to be an energy-efficient model for implementing program kernels. In this paper we explore the feasibility of using SC for more than small k...
Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea...
ICS
2005
Tsinghua U.
15 years 9 months ago
Think globally, search locally
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
Kamen Yotov, Keshav Pingali, Paul Stodghill
IPPS
2002
IEEE
15 years 9 months ago
Effective Cross-Platform, Multilevel Parallelism via Dynamic Adaptive Execution
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...
Walden Ko, Mark N. Yankelevsky, Dimitrios S. Nikol...
IEEEPACT
2000
IEEE
15 years 8 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany