Sciweavers

1133 search results - page 126 / 227
» Compiling for Speculative Architectures
Sort
View
IEEEPACT
2000
IEEE
15 years 8 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
LCTRTS
1999
Springer
15 years 8 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
APCSAC
2003
IEEE
15 years 8 months ago
On Implementing High Level Concurrency in Java
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...
G. Stewart Von Itzstein, Mark Jasiunas
DASIP
2010
14 years 11 months ago
Hardware code generation from dataflow programs
The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software archi...
Nicolas Siret, Matthieu Wipliez, Jean-Franç...
ASPLOS
2010
ACM
15 years 11 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...