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» Compiling for Speculative Architectures
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SPAA
2004
ACM
14 years 1 months ago
The potential in energy efficiency of a speculative chip-multiprocessor
While lower supply voltage is effective for energy reduction, it suffers performance loss. To mitigate the loss, we propose to execute only the part, which does not have any influ...
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
ICSE
2000
IEEE-ACM
14 years 8 hour ago
Software architecture: a roadmap
Over the past decade software architecture has received increasing attention as an important subfield of software engineering. During that time there has been considerable progres...
David Garlan
DAC
2003
ACM
14 years 9 months ago
Power-aware issue queue design for speculative instructions
Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the pe...
Tali Moreshet, R. Iris Bahar
ICCD
2007
IEEE
150views Hardware» more  ICCD 2007»
14 years 8 days ago
CAP: Criticality analysis for power-efficient speculative multithreading
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
James Tuck, Wei Liu, Josep Torrellas
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 1 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...