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CODES
1999
IEEE
14 years 24 days ago
A unified formal model of ISA and FSMD
In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor...
Jianwen Zhu, Daniel Gajski
DAC
2000
ACM
14 years 9 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
14 years 5 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore
ACSAC
2006
IEEE
14 years 2 months ago
Covert and Side Channels Due to Processor Architecture
Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show ...
Zhenghong Wang, Ruby B. Lee
ICCD
2000
IEEE
80views Hardware» more  ICCD 2000»
14 years 26 days ago
Power-Sensitive Multithreaded Architecture
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...
John S. Seng, Dean M. Tullsen, George Cai