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121
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ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
15 years 10 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
JOT
2006
113views more  JOT 2006»
15 years 3 months ago
Constraint Validation in Model Compilers
Model transformation has become one of the most focused research field, motivated by for instance the OMG's Model-Driven Architecture (MDA). Metamodeling is a central techniq...
László Lengyel, Tihamer Levendovszky...
ASYNC
2004
IEEE
121views Hardware» more  ASYNC 2004»
15 years 7 months ago
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis
We describe a new intermediate compiler representation, static token form, that is suitable for dataflow-style synthesis of high-level asynchronous specifications. Static token fo...
John Teifel, Rajit Manohar
133
Voted
FPL
2000
Springer
143views Hardware» more  FPL 2000»
15 years 7 months ago
Memory Access Schemes for Configurable Processors
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...
Holger Lange, Andreas Koch
HPCA
2004
IEEE
16 years 4 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti