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MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
15 years 10 months ago
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Dynamic software bug detection tools are commonly used because they leverage run-time information. However, they suffer from a fundamental limitation, the Path Coverage Problem: t...
Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep T...
ANSS
2007
IEEE
15 years 8 months ago
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiro...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 6 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ESTIMEDIA
2007
Springer
15 years 7 months ago
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
Matthias Hartmann, Vasileios (Vassilis) Pantazis, ...
SPAA
2010
ACM
15 years 4 months ago
Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures
We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling. Compared to previous multi-core stream scheduling algorithms, team schedu...
JongSoo Park, William J. Dally