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» Compiling for vector-thread architectures
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101
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SC
2004
ACM
15 years 8 months ago
Analysis and Performance Results of a Molecular Modeling Application on Merrimac
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. D...
EMSOFT
2004
Springer
15 years 8 months ago
Towards direct execution of esterel programs on reactive processors
Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediat...
Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Day...
100
Voted
LCTRTS
2004
Springer
15 years 8 months ago
Link-time optimization of ARM binaries
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
Bruno De Bus, Bjorn De Sutter, Ludo Van Put, Domin...
118
Voted
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 8 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
117
Voted
CGO
2003
IEEE
15 years 8 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz