Sciweavers

931 search results - page 49 / 187
» Compiling for vector-thread architectures
Sort
View
112
Voted
SAC
2010
ACM
15 years 9 months ago
A real-time architecture design language for multi-rate embedded control systems
This paper presents a language dedicated to the description of the software architecture of complex embedded control systems. The language relies on the synchronous approach but e...
Julien Forget, Frédéric Boniol, Davi...
113
Voted
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 6 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
CASES
2004
ACM
15 years 8 months ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
131
Voted
PDP
2002
IEEE
15 years 7 months ago
The CDAG: A Data Structure for Automatic Parallelization for a Multithreaded Architecture
Despite the explosive new interest in Distributed Computing, bringing software — particularly legacy software — to parallel platforms remains a daunting task. The Self Distrib...
Bernd Klauer, Frank Eschmann, Ronald Moore, Klaus ...
105
Voted
WIESS
2000
15 years 3 months ago
Stub-Code Performance Is Becoming Important
As IPC mechanisms become faster, stub-code efficiency becomes a performance issue for local client/server RPCs and inter-component communication. Inefficient and unnecessary compl...
Andreas Haeberlen, Jochen Liedtke, Yoonho Park, La...