931 search results - page 51 / 187 » Compiling for vector-thread architectures |
149
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CC
2009
Springer
15 years 10 days ago
2009
Springer
We present the architecture of the Rosser toolkit that allows optimisations to be specified in a domain specific language, then compiled and deployed towards optimising object prog...
108
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CASES
2003
ACM
15 years 7 months ago
2003
ACM
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
119
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ASPDAC
2008
ACM
15 years 4 months ago
2008
ACM
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
110
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PLDI
2004
ACM
15 years 8 months ago
2004
ACM
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
110
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ICCAD
2001
IEEE
15 years 11 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...