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» Compiling for vector-thread architectures
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130
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CODES
2007
IEEE
15 years 9 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
141
Voted
ICSE
2011
IEEE-ACM
14 years 6 months ago
Leveraging software architectures to guide and verify the development of sense/compute/control applications
A software architecture describes the structure of a computing system by specifying software components and their interactions. Mapping a software architecture to an implementatio...
Damien Cassou, Emilie Balland, Charles Consel, Jul...
101
Voted
DAC
2002
ACM
16 years 3 months ago
Retargetable binary utilities
Since software is playing an increasingly important role in systemon-chip, retargetable compilation has been an active research area in the last few years. However, the retargetti...
Maghsoud Abbaspour, Jianwen Zhu
125
Voted
DAC
2002
ACM
16 years 3 months ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...
IFIPPACT
1994
15 years 4 months ago
Exploiting the Parallelism Exposed by Partial Evaluation
: We describe an approach to parallel compilation that seeks to harness the vast amount of ne-grain parallelism that is exposed through partial evaluation of numerically-intensive ...
Rajeev J. Surati, Andrew A. Berlin