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DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 3 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 3 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
TIME
2005
IEEE
14 years 2 months ago
LOLA: Runtime Monitoring of Synchronous Systems
Abstract— We present a specification language and algorithms for the online and offline monitoring of synchronous systems including circuits and embedded systems. Such monitori...
Ben D'Angelo, Sriram Sankaranarayanan, Césa...
CF
2006
ACM
14 years 18 days ago
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
Juan del Cuvillo, Weirong Zhu, Guang R. Gao
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
14 years 14 days ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi