320 search results - page 10 / 64 » Completing design in use: closing the appropriation cycle |
ASYNC
2000
IEEE
13 years 11 months ago
2000
IEEE
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
VTC
2008
IEEE
14 years 1 months ago
2008
IEEE
—In this paper, a quality-of-service driven routing protocol is proposed for wireless cooperative networks. The key contribution of the proposed protocol is to bring the performa...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
FMCAD
2009
Springer
14 years 1 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...