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» Completion Energies and Scale
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ISLPED
2006
ACM
145views Hardware» more  ISLPED 2006»
14 years 4 months ago
An optimal analytical solution for processor speed control with thermal constraints
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
14 years 3 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 3 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
14 years 3 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...