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» Completion for Multiple Reduction Orderings
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AAAI
1996
13 years 11 months ago
Design and Implementation of a Replay Framework Based on a Partial Order Planner
In this paper we describe the design and implementation of the derivation replay framework, dersnlp+ebl (Derivational snlp+ebl), which is based within a partial order planner. der...
Laurie H. Ihrig, Subbarao Kambhampati
CADE
2010
Springer
13 years 10 months ago
A Slice-Based Decision Procedure for Type-Based Partial Orders
Automated software verification and path-sensitive program analysis require the ability to distinguish executable program paths from those that are infeasible. To achieve this, pro...
Elena Sherman, Brady J. Garvin, Matthew B. Dwyer
DAC
2003
ACM
14 years 3 months ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
SBCCI
2003
ACM
94views VLSI» more  SBCCI 2003»
14 years 3 months ago
A New Pipelined Array Architecture for Signed Multiplication
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
Eduardo A. C. da Costa, Sergio Bampi, José ...
ISMVL
2003
IEEE
80views Hardware» more  ISMVL 2003»
14 years 3 months ago
Augmented Sifting of Multiple-Valued Decision Diagrams
Discrete functions are now commonly represented by binary (BDD) and multiple-valued (MDD) decision diagrams. Sifting is an effective heuristic technique which applies adjacent var...
D. Michael Miller, Rolf Drechsler