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» Complexity Analysis of H.264 Decoder for FPGA Design
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ICMCS
2006
IEEE
142views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Complexity Analysis of H.264 Decoder for FPGA Design
— A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the ...
Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, T...
ASAP
2006
IEEE
150views Hardware» more  ASAP 2006»
13 years 9 months ago
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
Thomas Warsaw, Marcin Lukowiak
DSD
2007
IEEE
178views Hardware» more  DSD 2007»
14 years 1 months ago
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
Esra Sahin, Ilker Hamzaoglu
ASPDAC
2006
ACM
123views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Implementation of H.264/AVC decoder for mobile video applications
- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...
Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea ...
CODES
2005
IEEE
13 years 9 months ago
Hardware/software partitioning of software binaries: a case study of H.264 decode
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application’s binary are competitive with parti...
Greg Stitt, Frank Vahid, Gordon McGregor, Brian Ei...