This paper describes work in progress to develop a standard for interoperability among high-performance scientific components. This research stems from growing recognition that th...
Robert C. Armstrong, Dennis Gannon, Al Geist, Kata...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
Java is an attractive environment for writing portable message passing parallel programs. Considerable work in message passing interface bindings for the C and Fortran languages h...