We analyse the probability 1 − δ to be in an optimum solution after k steps of an inhomogeneous Markov chain which is specified by a logarithmic cooling schedule c(k) = Γ/ ln ...
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
This paper deals with the challenging problem of counting the number of solutions of a CSP, denoted #CSP. Recent progress have been made using search methods, such as BTD [15], whi...