271 search results - page 13 / 55 » Complexity-Effective Superscalar Processors |
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
CGO
2006
IEEE
14 years 1 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...