271 search results - page 29 / 55 » Complexity-Effective Superscalar Processors |
DFT
2008
IEEE
13 years 9 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
DATE
2003
IEEE
14 years 26 days ago
2003
IEEE
Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behavi...
VLDB
2005
ACM
14 years 1 months ago
2005
ACM
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
ISCA
2002
IEEE
14 years 15 days ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...