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MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 25 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
ASPLOS
2000
ACM
13 years 12 months ago
An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
Joshua Redstone, Susan J. Eggers, Henry M. Levy
JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 14 days ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 14 days ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith