271 search results - page 39 / 55 » Complexity-Effective Superscalar Processors |
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...