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» Complexity-Effective Superscalar Processors
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HIPEAC
2009
Springer
13 years 11 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...
PACS
2000
Springer
132views Hardware» more  PACS 2000»
13 years 11 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
HPCA
1995
IEEE
13 years 11 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
MAM
2002
63views more  MAM 2002»
13 years 7 months ago
OPTS: increasing branch prediction accuracy under context switch
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors. Though many dynamic branch predictors have been proposed to obtain high...
Moon-Sang Lee, Young-Jae Kang, Joonwon Lee, Seung ...