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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 7 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
FMCAD
2008
Springer
13 years 9 months ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse
AIPS
1998
13 years 8 months ago
Search Control of Plan Generation in Decision-Theoretic Planners
This paper addresses the search control problemof selecting whichplan to refine next for decision-theoretic planners, a choice point commonto the decision theoretic planners creat...
Richard Goodwin, Reid G. Simmons
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 1 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
CORR
2010
Springer
79views Education» more  CORR 2010»
13 years 7 months ago
Quantitative Games on Probabilistic Timed Automata
Abstract. Two-player zero-sum games are a well-established model for synthesising controllers that optimise some performance criterion. In such games one player represents the cont...
Marta Z. Kwiatkowska, Gethin Norman, Ashutosh Triv...