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DATE
2008
IEEE
204views Hardware» more  DATE 2008»
14 years 4 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
LCTRTS
2007
Springer
14 years 3 months ago
Generalizing parametric timing analysis
In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis tha...
Joel Coffman, Christopher A. Healy, Frank Mueller,...
ASPDAC
2006
ACM
101views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Worst case execution time analysis for synthesized hardware
- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on s...
Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You...
CHARME
1993
Springer
68views Hardware» more  CHARME 1993»
14 years 1 months ago
Temporal Analysis of Time Bounded Digital Systems
To perform veri cation of digital systems with time bounded delays, it is essential to characterize the space of all possible system behaviors. In this paper, we describe our analy...
Alan R. Martello, Steven P. Levitan
ASPDAC
2006
ACM
123views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
- We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent f...
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan...