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» Compress-and-conquer for optimal multicore computing
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DAC
2010
ACM
13 years 8 months ago
Virtual channels vs. multiple physical networks: a comparative analysis
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoi...
Young-Jin Yoon, Nicola Concer, Michele Petracca, L...
SPAA
2010
ACM
13 years 8 months ago
A universal construction for wait-free transaction friendly data structures
Given the sequential implementation of any data structure, we show how to obtain an efficient, wait-free implementation of that data structure shared by any fixed number of proces...
Phong Chuong, Faith Ellen, Vijaya Ramachandran
PVLDB
2011
13 years 3 months ago
Implementing Performance Competitive Logical Recovery
New hardware platforms, e.g. cloud, multi-core, etc., have led to a reconsideration of database system architecture. Our Deuteronomy project separates transactional functionality ...
David B. Lomet, Kostas Tzoumas, Michael J. Zwillin...
HPCA
2008
IEEE
14 years 8 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
PLDI
2010
ACM
14 years 1 months ago
Supporting speculative parallelization in the presence of dynamic data structures
The availability of multicore processors has led to significant interest in compiler techniques for speculative parallelization of sequential programs. Isolation of speculative s...
Chen Tian, Min Feng, Rajiv Gupta