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ISPASS
2010
IEEE
15 years 11 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
153
Voted
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 11 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
INFOCOM
2008
IEEE
15 years 11 months ago
Live Baiting for Service-Level DoS Attackers
Abstract. Denial-of-Service (DoS) attacks remain a challenging problem in the Internet. In a DoS attack the attacker is attempting to make a resource unavailable to its intended le...
Sherif M. Khattab, Sameh Gobriel, Rami G. Melhem, ...
SMC
2007
IEEE
111views Control Systems» more  SMC 2007»
15 years 11 months ago
Prediction method to maintain QoS in weather impacted wireless and satellite networks
—Rain and snow can have a distorting effect on Ku and Ka bands signal fidelity resulting in excessive digital transmission errors. This loss of signal attenuation is commonly ref...
Kamal Harb, Anand Srinivasan, Changcheng Huang, Br...
CODES
2003
IEEE
15 years 10 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
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