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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
14 years 1 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
CP
2004
Springer
14 years 26 days ago
ID Walk: A Candidate List Strategy with a Simple Diversification Device
This paper presents a new optimization metaheuristic called ID Walk (Intensification/Diversification Walk) that offers advantages for combining simplicity with effectiveness. In ad...
Bertrand Neveu, Gilles Trombettoni, Fred Glover
LISA
2008
13 years 11 months ago
Portable Desktop Applications Based on P2P Transportation and Virtualization
Play-on-demand is usually regarded as a feasible access mode for web content (including streaming video, web pages and so on), web services and some Software-As-A-Service (SaaS) a...
Youhui Zhang, Xiaoling Wang, Liang Hong
ASPLOS
2008
ACM
13 years 11 months ago
No "power" struggles: coordinated multi-level power management for the data center
Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different ...
Ramya Raghavendra, Parthasarathy Ranganathan, Vani...
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