503 search results - page 5 / 101 » Computational Efficiency Evaluation in Output Analysis |
AINA
2005
IEEE
14 years 1 months ago
2005
IEEE
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
ACL
2004
13 years 8 months ago
2004
We show that a practical translation of MRS descriptions into normal dominance constraints is feasible. We start from a recent theoretical translation and verify its assumptions o...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
STACS
2010
Springer
14 years 2 months ago
2010
Springer
We construct efficient data structures that are resilient against a constant fraction of adversarial noise. Our model requires that the decoder answers most queries correctly with...
AMC
2006
13 years 7 months ago
2006
Missing values in inputs, outputs cannot be handled by the original data envelopment analysis (DEA) models. In this paper we introduce an approach based on interval DEA that allow...